/*
 * Copyright (c) 2006-2021, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2011-12-05     Bernard      the first version
 * 2011-04-02     prife        add mark_badblock and check_block
 * 2021-06-25     THEWON       add nand flash general purpose interface
 */

/*
 * COPYRIGHT (C) 2012, Shanghai Real Thread
 */

#ifndef __MTD_NAND_H__
#define __MTD_NAND_H__

#include <rtdevice.h>
#include "board.h"

#define RT_MTD_EOK          0     /* NO error */
#define RT_MTD_EECC         101   /* ECC error */
#define RT_MTD_EBUSY        102   /* hardware busy */
#define RT_MTD_EIO          103   /* generic IO issue */
#define RT_MTD_ENOMEM       104   /* out of memory */
#define RT_MTD_ESRC         105   /* source issue */
#define RT_MTD_EECC_CORRECT 106   /* ECC error but correct */

/* MTD control cmd types */
typedef enum
{
    RT_MTD_CTRL_GET_ID = 0,
    RT_MTD_CTRL_ERASE,
    RT_MTD_CTRL_CHECK,
    RT_MTD_CTRL_MARK,
    RT_MTD_CTRL_READ,
    RT_MTD_CTRL_WRITE,
} rt_mtd_cmd_t;

/* NAND Flash control cmd types */
typedef enum
{
    RT_NAND_CMD_PAGE_RD,           /* read data to chip's page buffer, do WaitBusy after this cmd in low driver */
    RT_NAND_CMD_PAGE_WR_BGN,       /* write data to chip's page buffer */
    RT_NAND_CMD_PAGE_WR_END,       /* do flash programe */
    RT_NAND_CMD_BLK_ERASE,         /* erase block */
    RT_NAND_CMD_ECC_EN,            /* enable gen HWECC */
    RT_NAND_CMD_ECC_DIS            /* disable gen HWECC */
} rt_nand_cmd_t;

typedef struct rt_nand_driver *rt_nand_driver_t;
struct rt_nand_driver_ops;

#define RT_MTD_NAND_DEVICE(device)  ((struct rt_mtd_nand_device*)(device))

struct rt_mtd_nand_driver_ops;

struct rt_mtd_nand_device
{
    struct rt_device parent;

    rt_size_t total_size;
    rt_uint16_t page_size;          /* The Page size in the flash */
    rt_uint16_t oob_size;           /* Out of bank size */
    rt_uint16_t oob_free;           /* the free area in oob that flash driver not use */
    rt_uint16_t plane_num;          /* the number of plane in the NAND Flash */

    rt_uint16_t pages_per_block;    /* The number of page a block */
    rt_uint16_t block_total;

    /* Only be touched by driver */
    rt_uint16_t block_start;        /* The start of available block */
    rt_uint16_t block_end;          /* The end of available block */

    /* operations interface */
    const struct rt_mtd_nand_driver_ops *ops;

    void *priv;
};
typedef struct rt_mtd_nand_device *rt_mtd_nand_t;

struct rt_mtd_nand_driver_ops
{
    rt_uint32_t (*read_id)();
    rt_err_t (*read_page)(rt_mtd_nand_t device,
                          rt_off_t page,
                          rt_uint8_t *data, rt_uint32_t data_len,
                          rt_uint8_t *spare, rt_uint32_t spare_len);

    rt_err_t (*write_page)(struct rt_mtd_nand_device *device,
                           rt_off_t page,
                           const rt_uint8_t *data, rt_uint32_t data_len,
                           const rt_uint8_t *spare, rt_uint32_t spare_len);
    rt_err_t (*move_page)(struct rt_mtd_nand_device *device, rt_off_t src_page, rt_off_t dst_page);

    rt_err_t (*erase_block)(struct rt_mtd_nand_device *device, rt_int32_t block);
    rt_err_t (*check_block)(struct rt_mtd_nand_device *device, rt_int32_t block);
    rt_err_t (*mark_badblock)(struct rt_mtd_nand_device *device, rt_int32_t block);
};

struct rt_mtd_nand_rw_args
{
    rt_off_t page;
    rt_uint8_t *data;
    rt_uint32_t data_len;
    rt_uint8_t *spare;
    rt_uint32_t spare_len;
};

struct rt_mtd_oob_region
{
    rt_uint8_t offset;
    rt_uint8_t length;
};

struct rt_nand_ecc
{
    rt_uint8_t ecc_bytes;             /* gen ecc bytes per ecc step(usually 3) */
    rt_uint16_t ecc_stepsize:12;      /* min 256 */
    rt_uint16_t ecc_step:4;           /* ecc step */

    /* driver must set the two interface if HWECC */
    void (*calculate)(rt_nand_driver_t chip, const rt_uint8_t *data, rt_uint8_t *ecc_code);
    /* return max bit flips if can't correct,return -1 ECC is error(0 success) */
    int (*correct)(rt_nand_driver_t chip, rt_uint8_t *data, rt_uint8_t *ecc_read, rt_uint8_t *ecc_calc);
    /* ignore if NONECC */
    const struct rt_mtd_oob_region *layout;
};

struct rt_nand_buffers
{
    rt_uint8_t *oob_poi;
    rt_uint8_t *pagebuf;
    rt_uint8_t *ecc_calc;
    rt_uint8_t *ecc_code;
};

struct rt_nand_driver
{
    struct rt_mtd_nand_device parent;

    /* driver must init these */
    struct rt_nand_ecc ecc;
    const struct rt_nand_driver_ops *ops;
    const struct rt_mtd_oob_region *free_layout;

    /* driver do not touch */
    struct rt_nand_buffers buffers;
};

struct rt_nand_driver_ops
{
    rt_uint32_t (*read_id)(void);

    rt_err_t (*cmdfunc)(rt_nand_driver_t nand, int cmd, int page, int offset);     /* send nand operation cmd, return Status bits(0 success),
                                                                               if nand is busy please wait in low driver */
    rt_err_t (*read_buf)(rt_nand_driver_t nand, rt_uint8_t *buf, int len);         /* read data from nand chip's page buffer */
    rt_err_t (*write_buf)(rt_nand_driver_t nand, const rt_uint8_t *buf, int len);  /* write data to nand chip's page buffer */
    rt_err_t (*checkbad)(rt_nand_driver_t nand, rt_uint32_t blk);                  /* if NULL OOB[0] used as bad mark(not 0xff is bad) */
    rt_err_t (*markbad)(rt_nand_driver_t nand, rt_uint32_t blk);                   /* if NULL OOB[0] used as bad mark(set to 0x00) */
};

rt_err_t rt_mtd_nand_register_device(const char *name, struct rt_mtd_nand_device *device);

#if defined(RT_MTD_NAND_DEBUG) && defined(RT_USING_FINSH)
rt_inline rt_uint32_t rt_mtd_nand_read_id(struct rt_mtd_nand_device *device)
{
    rt_uint32_t id;
    RT_ASSERT(device->ops->read_id);
    id = device->ops->read_id();
    rt_kprintf("nand id: 0x%08x", id);
    return 0;
}

rt_inline rt_err_t rt_mtd_nand_read(
    struct rt_mtd_nand_device *device,
    rt_off_t page,
    rt_uint8_t *data, rt_uint32_t data_len,
    rt_uint8_t *spare, rt_uint32_t spare_len)
{
    RT_ASSERT(device->ops->read_page);
    return device->ops->read_page(device, page, data, data_len, spare, spare_len);
}

rt_inline rt_err_t rt_mtd_nand_write(
    struct rt_mtd_nand_device *device,
    rt_off_t page,
    const rt_uint8_t *data, rt_uint32_t data_len,
    const rt_uint8_t *spare, rt_uint32_t spare_len)
{
    RT_ASSERT(device->ops->write_page);
    return device->ops->write_page(device, page, data, data_len, spare, spare_len);
}

rt_inline rt_err_t rt_mtd_nand_move_page(struct rt_mtd_nand_device *device,
        rt_off_t src_page, rt_off_t dst_page)
{
    RT_ASSERT(device->ops->move_page);
    return device->ops->move_page(device, src_page, dst_page);
}

rt_inline rt_err_t rt_mtd_nand_erase_block(struct rt_mtd_nand_device *device, rt_uint32_t block)
{
    RT_ASSERT(device->ops->erase_block);
    return device->ops->erase_block(device, block);
}

rt_inline rt_err_t rt_mtd_nand_check_block(struct rt_mtd_nand_device *device, rt_uint32_t block)
{
    if (device->ops->check_block)
    {
        return device->ops->check_block(device, block);
    }
    else
    {
        return -RT_ENOSYS;
    }
}

rt_inline rt_err_t rt_mtd_nand_mark_badblock(struct rt_mtd_nand_device *device, rt_uint32_t block)
{
    if (device->ops->mark_badblock)
    {
        return device->ops->mark_badblock(device, block);
    }
    else
    {
        return -RT_ENOSYS;
    }
}
#endif /* defined(RT_MTD_NAND_DEBUG) && defined(RT_USING_FINSH) */

#endif /* MTD_NAND_H_ */
